Where Tinit is the time taken to initialize the T6963C
Figure 7.1: Power Supply Sequence
To prevent latch-up of the CMOS LSI (T6963C and LCD driver LSI) ensure your system power supply follows the following sequence. It is very important to follow this sequence in order to prevent the CMOS LSI from latching up and to prevent DC signals from being applied to the LC material. If the VEE voltage is applied before timing signals M, CL1, CL2, and FLM then a DC voltage signal will be applied to the LC material. Over time this will degrade the LC fluid performance due to an electro-chemical effect. If this power-up sequence is not adherred to, permanent damage to the LCD module may result.
After power on it is necessary to keep /RES terminal low for six oscillator clock cycles to ensure proper reset of the T6963C. If T6963C is reset during normal operation ensure that the VEE voltage to the LCD is disabled until the T6963C registers are re-initialized.
Where Tinit is the time taken to initialize the T6963C
Figure 7.1: Power Supply Sequence
The T6963C may be reset by an external active low TTL signal from a MPU or other logic
device or it may be reset using the following circuit.
Figure 7.2: RESET Circuit
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